Hardware manual

Microcomputer Technical Q&A
62
Q&A No.: QAH8S-053
Category: Electrical Characteristics
Subject: RD Signal Timing
Question
With successive read cycles, does the RD signal go high momentarily when the bus cycle changes,
or does it remain low?
Answer
The RD signal goes high momentarily. The RD signal rise delay time t
RSD2
and fall delay time t
RSD1
are virtually the same (t
RSD1
t
RSD2
). Therefore, the high-level width of the RD signal is as follows:
Since t
RSD1
t
RSD2
,
RD signal high-level width = (t
cyc
/2) + t
RSD1
– t
RSD2
(t
cyc
/2)
T1
T2 T3
φ
A23 to A0
t
AD
t
RSD2
Hi
g
h-level width
t
AS
t
RSD1
t
RSD2
RD
RD Signal Timing