Hardware manual

Microcomputer Technical Q&A
54
Q&A No.: QAH8S-045
Category: Power-Down State
Subject: Medium-Speed Mode
Question
Why is it that, in medium-speed mode, a divided clock is supplied to the bus masters (CPU, DTC,
DMAC), while the original system clock is supplied to the other on-chip supporting modules?
Answer
The internal clock supplied to the on-chip supporting modules is always fixed. Therefore, if
medium-speed mode is set during SCI transmission/reception, for example, SCI operation will
continue normally even though the bus master clock is changed. Medium-speed mode can thus be
set at any time without regard to the operation of the on-chip supporting modules.
Also, non-operating modules can be stopped individually by means of the module stop function.
Applicable Products
Applicability Series Applicability Series Applicability Series
Yes Entire H8S Series H8S/2655 H8S/2350
H8S/2355 H8S/2357 H8S/2345
H8S/2245 H8S/2148 H8S/2144
H8S/2138 H8S/2134 H8S/2128
H8S/2124 — — — —