Hardware manual

Microcomputer Technical Q&A
52
Q&A No.: QAH8S-044
Category: Bus Controller
Subject: 2-CAS DRAM Interface
Question
Please explain the use of the LCASS bit with the 2-CAS DRAM interface.
Answer
The LCASS bit in bus control register L (BCRL) selects whether the LWR pin or the LCAS pin is
used for the LCAS signal on the 2-CAS DRAM interface.
LCASS Description
0 The LCAS pin is used for the 2-CAS DRAM interface LCAS signal.
• More pins are needed for bus control. (BREQO output and WAIT input cannot be
used.)
• RAS down mode can be used, and DRAM fast page mode can be used
effectively.
• CBR refreshing can be performed in parallel with ordinary space access, limiting
the drop in performance due to refreshing.
• An idle cycle is not necessary in CBR refreshing after DRAM access.
• Compatible with H8S/2350 Series
1 The LWR pin is used for the 2-CAS DRAM interface LCAS signal. (Initial value)
• Fewer pins are needed for bus control. (BREQO output and WAIT input can be
used.)
• RAS down mode cannot be used.
• Another ordinary space access cannot be performed during the CBR refresh
period.
• An idle cycle is inserted in CBR refreshing after DRAM access.
• Not compatible with H8S/2350 Series
Clearing the LCASS bit to 0 and using the LCAS pin for the LCAS signal enables DRAM to be
accessed efficiently.