Hardware manual

ii
Subject: Use of Different Interrupt Modes................................................................................... 33
Subject: Insufficient Number of External Interrupts.................................................................... 35
Bus controller
Subject: CS State in On-Chip RAM and Internal I/O Access...................................................... 36
Subject: φ Clock State when Bus is Released .............................................................................. 37
Subject: WAIT (1)........................................................................................................................ 38
Subject: WAIT (2)........................................................................................................................ 39
Subject: Program Wait Switchover Timing ................................................................................. 41
Subject: BREQ Acceptance in Power-Down Modes ................................................................... 43
Subject: External Connection of RAM to 8-Bit-Access Space.................................................... 44
Subject: Bus Controller Settings for Area 7................................................................................. 45
Subject: External Bus states during CPU Operation.................................................................... 47
Subject: Internal I/O Register Access when Bus is Released ...................................................... 48
Subject: CS Signals after Power-On Reset................................................................................... 49
Subject: Bus Release Wait Time after BREQ Input .................................................................... 50
Subject: External Bus Right Release and Refresh Control .......................................................... 51
Subject: 2-CAS DRAM Interface ................................................................................................ 52
Power-Down State
Subject: Medium-Speed Mode..................................................................................................... 54
Subject: Oscillation Settling Wait Time after Software Standby Mode ...................................... 55
Subject: On-Chip Supporting Modules in Software Standby Mode............................................ 56
Subject: Mode Pins (MD2 to MD0) in Hardware Standby Mode................................................ 57
Subject: Hardware Standby Mode at Power-On .......................................................................... 58
Subject: Module Stop Mode......................................................................................................... 59
Subject: Timer Output in Module Stop Mode.............................................................................. 60
Electrical Characteristics
Subject: Current Dissipation Value..............................................................................................61
Subject: RD Signal Timing .......................................................................................................... 62
Pins
Subject: Handling of Unused Pins................................................................................................64
Subject: RES Pin, STBY Pin, and NMI Pin Input Circuits.......................................................... 65
Subject: Address Pin States in On-Chip Memory Access............................................................ 66
Subject: Built-In MOS Pull-Ups in Reset .................................................................................... 68
Subject: WDTOVF Pin ................................................................................................................ 69