Hardware manual

Microcomputer Technical Q&A
45
Q&A No.: QAH8S-038
Category: Bus Controller
Subject: Bus Controller Settings for Area 7
Question
Area 7 includes a mix of on-chip RAM and internal I/O registers. For which areas are the bus
width and number of access states set in the bus controller valid?
Answer
In area 7, the bus width and number of access states set in the bus controller are valid for areas
other than on-chip RAM and internal I/O registers*. The bus width and number of access states for
on-chip RAM and on-chip supporting modules are fixed as shown in the table below.
Note: * Depends on the product; see the relevant hardware manual for details.
CPU bus Interface (Example of H8S/2655)
On-Chip Modules On-Chip Memory
On-Chip Supporting Modules Bus Width Access Bus Width Access
A/D, TPU, 8-bit timers, WDT 16 bits 2 states 16 bits 1 state
Others 8 bits
When the RAME bit is cleared to 0 in the system control register (SYSCR), on-chip RAM is
disabled, and the area 7 settings are followed. In this case, the CS7 signal goes low for the area 7
RAM area.