Hardware manual

Microcomputer Technical Q&A
37
Q&A No.: QAH8S-032
Category: Bus Controller
Subject: φ Clock State when Bus is Released
Question
Is the φ clock output when the bus is released?
Answer
If the corresponding port data direction register (DDR) bit is set to 1 and the PSTOP bit in the
system control register (SYSCR) is cleared to 0, the φ clock is output when the bus is released.
Applicable Products
Applicability Series Applicability Series Applicability Series
Entire H8S Series Yes H8S/2655 Yes H8S/2350
Yes H8S/2355 Yes H8S/2357 Yes H8S/2345
Yes H8S/2245 H8S/2148 H8S/2144
H8S/2138 H8S/2134 H8S/2128
H8S/2124 — — — —