Hardware manual

Microcomputer Technical Q&A

Q&A No.: QAH8S-023

Category: Interrupts

Subject: Handling of Interrupt Requests when Interrupts are Masked

Question

Is an IRQnF interrupt request held pending if generated when interrupts are masked by the I and

UI bits, or bits I2 to I0, in the condition code register (CCR)?

Answer

Yes. IRQnF is independent of the status of the I and UI bits. If interrupt masking is released while

the IRQnF and IRQnE bits are set to 1, the interrupt will be accepted.

Applicable Products

Applicability Series Applicability Series Applicability Series

Yes Entire H8S Series H8S/2655 H8S/2350

H8S/2355 H8S/2357 H8S/2345

H8S/2245 H8S/2148 H8S/2144

H8S/2138 H8S/2134 H8S/2128

H8S/2124 — — — —