Hardware manual

Microcomputer Technical Q&A

Q&A No.: QAH8S-022

Category: Interrupts

Subject: Handling of Interrupt Requests when IRQ Interrupts are

Disabled

Question

Is an IRQn interrupt request held pending if generated while the IRQnE bit is cleared to 0 in the

IRQ enable register (IER)?

Answer

Yes. When the signal specified in the IRQ sense control register (ISCR) is input to the IRQn pin,

IRQnF (the IRQn flag) is set to 1 in the IRQ status register (ISR). This does not depend on the

status of the IRQnE bit. If the IRQnE bit is set to 1 while IRQnF is set to 1, an interrupt is

requested. IRQnF can be cleared to 0 by software.

Applicable Products

Applicability Series Applicability Series Applicability Series

Yes Entire H8S Series H8S/2655 H8S/2350

H8S/2355 H8S/2357 H8S/2345

H8S/2245 H8S/2148 H8S/2144

H8S/2138 H8S/2134 H8S/2128

H8S/2124 — — — —