Hardware manual

Microcomputer Technical Q&A
124
Answers
The TDRE set timing differs depending on whether or not the transmit shift register (TSR)
contains transmit data.
1. Asynchronous mode
a. When TSR contains transmit data (see figure below)
1234567891011121314151612345678910111213141516
Stop bit Start bit
Base clock
Transmit
data
TDRE
When SCK clock source is internal clock: 4 states
When SCK clock source is external clock: 4 to 5 states
This timing also applies when transmission is started by setting the TE (transmit enable)
bit.