Hardware manual

Microcomputer Technical Q&A
111
Answers
1. The RDRF flag is set following the fall of the data sampling clock after the stop bit data is
received (see figure below).
1234567891011121314151612345678910111213141516
Bit 7 Stop bit
Base clock
Receive data
Data sampling
RDRF
When SCK clock source is internal clock: 0.5 base clock + 2 states
When SCK clock source is external clock: 3 to 4 states
With 8-Bit Data and 1 Stop Bit