Hardware manual

Microcomputer Technical Q&A
107
01234
0 123 4 567P
5 5 6 7 8 150 1 5 6 7 8 1415013
16 clocks
160 clocks
Start Stop Start
TYP. A B CLK RxD (Typ) RxD (Typ) RxD (Min) RxD (A) SYNC DATA sample
Start bit Start bit Start bit Start bit
Sampling drift: 1 clock max.
Stop
Stop bit
Stop bit
Sampling possible even with 7.5-clock drift
With bit drift
Sampling drift: 1 clock max.
1 clock
Stop bit
Error will result if stop bit cannot be sampled here
= +7.5/160 = –7/160
With bit drift Enlarged diagram
Sampling possible even with 7-clock drift
Receive Margins in Asynchronous Mode