Hardware manual

Microcomputer Technical Q&A
106
Q&A No.: QAH8S-231
Category: SCI
Subject: Permissible Bit Rate Error in Asynchronous Mode
Question
What is the permissible bit rate error in asynchronous mode?
Answer
When the H8S Series chip is receiving, the permissible error within one frame is as shown below.
This shows the worst case for the sampling timing of the last bit (stop bit) of the frame. With 8-bit
data and no parity, one frame consists of 160 internal basic clocks. Assuming no per-bit distortion,
the conditions under which the stop bit can be sampled are as follows:
• When transmitting side is slow: 7.5/160 = 0.046
• When transmitting side is fast: –7/160 = –0.043
From the above two points, the permissible error can be calculated to be approximately 4.3%
This is a theoretical value. A margin should be allowed on the system side in actual system
designs.