87
SCK0, SCK1
t
SCKW
t
SCKr
t
SCKf
t
Scyc
Figure 22.21 SCK Clock Input Timing
TxD0, TxD1
(transmit data)
RxD0, RxD1
(receive data)
SCK0, SCK1
t
RXS
t
RXH
t
TXD
Figure 22.22 SCI Input/Output Timing (Synchronous Mode)
ΓΈ
ADTRG
t
TRGS
Figure 22.23 A/D Converter External Trigger Input Timing
