Product data

84
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
TMR Timer output
delay time
t
TMOD
50 50 100 ns Figure
22.17
Timer reset input
setup time
t
TMRS
30 30 50 Figure
22.19
Timer clock input
setup time
t
TMCS
30 30 50 Figure
22.18
Timer
clock
Single
edge
t
TMCWH
1.5 1.5 1.5 t
cyc
pulse
width
Both
edges
t
TMCWL
2.5 2.5 2.5
PWM,
PWMX
Pulse output
delay time
t
PWOD
50 50 100 ns Figure
22.20
SCI Input
clock
Asynchro-
nous
t
Scyc
4— 4— 4— t
cyc
Figure
22.21
cycle
Synchro-
nous
6— 6— 6—
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise
time
t
SCKr
1.5 1.5 1.5 t
cyc
Input clock fall
time
t
SCKf
1.5 1.5 1.5
Transmit data
delay time
(synchronous)
t
TXD
50 50 100 ns Figure
22.22
Receive data
setup time
(synchronous)
t
RXS
50 50 100 ns
Receive data
hold time
(synchronous)
t
RXH
50 50 100 ns
A/D
converter
Trigger input
setup time
t
TRGS
30 30 50 ns Figure
22.23
Notes: 1. Only supporting modules that can be used in subclock operation
2. For the low-voltage F-ZTAT version, V
CC
= 3.0 V to 5.5 V