Product data

76
(3) Bus Timing
Table 22.8 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (ø = 32.768 kHz).
Table 22.8 Bus Timing
Condition A: V
CC
= 5.0 V ± 10%, V
SS
= 0 V, ø = 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition B: V
CC
= 4.0 V to 5.5 V, V
SS
= 0 V, ø = 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition C: V
CC
= 2.7 V to 5.5 V*, V
SS
= 0 V, ø = 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Address
delay time
t
AD
— 20 — 30 — 40 ns Figure 22.9
to
Address
setup time
t
AS
0.5 ×
t
cyc
– 15
— 0.5 ×
t
cyc
– 20
— 0.5 ×
t
cyc
– 30
—ns
figure 22.13
Address
hold time
t
AH
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 15
— 0.5 ×
t
cyc
– 20
—ns
CS delay
time (IOS)
t
CSD
—20 —30 —40 ns
AS delay
time
t
ASD
—30 —45 —60 ns
RD delay
time 1
t
RSD1
—30 —45 —60 ns
RD delay
time 2
t
RSD2
—30 —45 —60 ns
Read data
setup time
t
RDS
15 — 20 — 35 — ns
Read data
hold time
t
RDH
0— 0— 0— ns
Read data
access time 1
t
ACC1
— 1.0 ×
t
cyc
– 30
— 1.0 ×
t
cyc
– 40
— 1.0 ×
t
cyc
– 60
ns
Read data
access time 2
t
ACC2
— 1.5 ×
t
cyc
– 25
— 1.5 ×
t
cyc
– 35
— 1.5 ×
t
cyc
– 50
ns