Product data
50
16.4 Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 16.6 I
2
C Bus Timing (SCL and SDA Output)
Item Symbol Output Timing Unit Notes
SCL output cycle time t
SCLO
28t
cyc
to 256t
cyc
ns Figure 22.24
SCL output high pulse width t
SCLHO
0.5t
SCLO
ns
(reference)
SCL output low pulse width t
SCLLO
0.5t
SCLO
ns
SDA output bus free time t
BUFO
0.5t
SCLO
– 1t
cyc
ns
Start condition output hold time t
STAHO
0.5t
SCLO
– 1t
cyc
ns
Retransmission start condition output
setup time
t
STASO
1t
SCLO
ns
Stop condition output setup time t
STOSO
0.5t
SCLO
+ 2t
cyc
ns
Data output setup time (master) t
SDASO
1t
SCLLO
– 3t
cyc
ns
Data output setup time (slave) 1t
SCLL
– (6t
cyc
or 12t
cyc
*)
Data output hold time t
SDAHO
3t
cyc
ns
Note: * 6t
cyc
when IICX is 0, 12t
cyc
when 1.
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in I
2
C Bus Timing in section 22,
Electrical Characteristics. Note that the I
2
C bus interface AC timing specifications will not be
met with a system clock frequency of less than 5 MHz.