Product data

48
Slave transmit mode
Write transmit data in ICDR
Read IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read ACKB in ICSR
Set TRS = 0 in ICCR
End
of transmission
(ACKB = 1)?
Yes
No
No
Yes
End
[1]
[2]
[3]
Read ICDR
[5]
[4]
[1] Set transmit data for the second and
subsequent bytes.
[2] Wait for 1 byte to be transmitted.
[3] Test for end of transfer.
[4] Select slave receive mode.
[5] Dummy read (to release the SCL line).
Figure 16.17 Flowchart for Slave Transmit Mode (Example)
16.3.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 16.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• TDRE and RDRF internal flags
• Transmit/receive sequencer and internal operating clock counter