Product data
36
9
A Bit7
Master receive modeMaster transmit mode
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
[2] ICDR read
(dummy read)
[2] IRIC clear [4] IRIC clear [6] ICDR read
(Data 1)
[7] IRIC clear
Bit6 Bit5 Bit4 Bit3 Bit7 Bit6 Bit5 Bit4 Bit3Bit2 Bit1 Bit0
12 34 56 78
[3] [5]
A
912 345
Data 1 Data 2
Data 1
Figure 16.8 (a) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
8
Bit0
Data 2
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [9] IRIC clear [6] ICDR read
(Data 2)
[7] IRIC clear [9] IRIC Clear [6] ICDR read
(Data 3)
[7] IRIC clear
Bit7
[8] [5]
A
Bit6 Bit5 Bit4 Bit7 Bit6Bit3 Bit2 Bit1 Bit0
91 23 45 67
[8] [5]
A
8912
Data 3 Data 4
Data 3Data 2Data 1
Figure 16.8 (b) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)