Product data

26
16.2.7 Serial/Timer Control Register (STCR)
Bit
Initial value
Read/Write
7
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
0
R/W
1
ICKS1
0
R/W
STCR is an 8-bit readable/writable register that controls register access, the I
2
C interface operating
mode (when the on-chip IIC option is included), and on-chip flash memory (F-ZTAT versions),
and selects the TCNT input clock source. For details of functions not related to the I
2
C bus
interface, see section 3.2.4, Serial/Timer Control Register (STCR), and the descriptions of the
relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding
bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not write 1 to this bit.
Bit 6 and 5—I
2
C Transfer Select 1 and 0 (IICX1 and 0): This bit, together with bits CKS2 to
CKS0 in ICMR, selects the transfer rate in master mode. For details, see section 16.2.4, I
2
C Bus
Mode Register (ICMR).
Bit 4—I
2
C Master Enable (IICE): Controls CPU access to the I
2
C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX data and control registers, and SCI
control registers.
Bit 4
IICE Description
0 CPU access to I
2
C bus interface data and control registers is disabled
CPU access to SCI control registers is enabled
(Initial value)
1 CPU access to I
2
C bus interface data and control registers is enabled
CPU access to PWMX data and control registers is enabled
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting module
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details.
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see
section 12.2.4, Timer Control Register (TCR).