Product data
151
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
TMR Timer output
delay time
t
TMOD
— 50 — 50 — 100 ns Figure
22.66
Timer reset input
setup time
t
TMRS
30 — 30 — 50 — Figure
22.68
Timer clock input
setup time
t
TMCS
30 — 30 — 50 — Figure
22.67
Timer
clock
Single
edge
t
TMCWH
1.5 — 1.5 — 1.5 — t
cyc
pulse
width
Both
edges
t
TMCWL
2.5 — 2.5 — 2.5 —
SCI Input
clock
Asynchro-
nous
t
Scyc
4— 4— 4— t
cyc
Figure
22.69
cycle
Synchro-
nous
6— 6— 6—
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise
time
t
SCKr
— 1.5 — 1.5 — 1.5 t
cyc
Input clock fall
time
t
SCKf
— 1.5 — 1.5 — 1.5
Transmit data
delay time
(synchronous)
t
TXD
— 50 — 50 — 100 ns Figure
22.70
Receive data setup
time (synchronous)
t
RXS
50 — 50 — 100 — ns
Receive data hold
time (synchronous)
t
RXH
50 — 50 — 100 — ns
A/D
con-
verter
Trigger input setup
time
t
TRGS
30 — 30 — 50 — ns Figure
22.71
Note: * Only supporting modules that can be used in subclock operation