Product data

124
Table 22.22 I
2
C Bus Timing
Conditions: V
CC
= 4.0 V to 5.5 V, V
CC
= 2.7 V to 3.6 V (3 V version), V
SS
= 0 V, ø = 5 MHz to
maximum operating frequency, T
a
= –20 to +75°C
Item Symbol Min Typ Max Unit Test Conditions Notes
SCL clock cycle
time
t
SCL
12 ——t
cyc
Figure 22.48
SCL clock high
pulse width
t
SCLH
3 ——t
cyc
SCL clock low
pulse width
t
SCLL
5 ——t
cyc
SCL, SDA input
rise time
t
Sr
7.5
*
t
cyc
SCL, SDA input
fall time
t
Sf
300 ns
SCL, SDA input
spike pulse
elimination time
t
SP
——1t
cyc
SDA input bus
free time
t
BUF
5 ——t
cyc
Start condition
input hold time
t
STAH
3 ——t
cyc
Retransmission
start condition
input setup time
t
STAS
3 ——t
cyc
Stop condition
input setup time
t
STOS
3 ——t
cyc
Data input setup
time
t
SDAS
0.5 t
cyc
Data input hold
time
t
SDAH
0 ——ns
SCL, SDA
capacitive load
C
b
400 pF
Note: * 17.5t
cyc
can be set according to the clock selected for use by the I
2
C module. For details,
see section 16.4, Usage Notes.