Product data
3
ΓΈ
PS
Noise
canceler
Noise
canceler
Clock
control
Formatless dedicated
clock (channel 0 only)
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Address
comparator
SAR, SARX
Interrupt
generator
ICDRS
ICDRR
ICDRT
ICSR
ICMR
ICCR
Internal data bus
Interrupt
request
SCL
SDA
Legend:
ICCR:
ICMR:
ICSR:
ICDR:
SAR:
SARX:
PS:
I
2
C bus control register
I
2
C bus mode register
I
2
C bus status register
I
2
C bus data register
Slave address register
Second slave address register
Prescaler
Figure 16.1 Block Diagram of I
2
C Bus Interface