Product data
101
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2128S Series, P52/SCK0 and P47 (ICE = 0) high levels are driven by
NMOS.
*5 The upper limit of the port 6 applied voltage is V
CC
+ 0.3 V when CIN input is not
selected, and the lower of V
CC
+ 0.3 V and AV
CC
+ 0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
*6 Current dissipation values are for V
IH
min = V
CC
– 0.2 V and V
IL
max = 0.2 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
*7 The values are for V
RAM
≤ V
CC
< 4.0 V, V
IH
min = V
CC
− 0.2 V, and V
IL
max = 0.2 V.
*8 The V
T
+
to V
T
–
specification does not apply to IRQ2 (ADTRG) to IRQ0.