Product data

93
Item Symbol Min Typ Max Unit
Test
Condition
Erase Wait time after
SWE-bit setting
*
1
x 10——µs
Wait time after
ESU-bit setting
*
1
y 200 — — µs
Wait time after
E-bit setting
*
1
*
6
z5—10ms
Wait time after
E-bit clear
*
1
α 10——µs
Wait time after
ESU-bit clear
*
1
β 10——µs
Wait time after
EV-bit setting
*
1
γ 20——µs
Wait time after
dummy write
*
1
ε 2 ——µs
Wait time after
EV-bit clear
*
1
η 5 ——µs
Maximum erase
count
*
1
*
6
*
7
N — — 120 Times z = 10 ms
Notes: *1 Set the times according to the program/erase algorithms.
*2 Programming time per 32 bytes (Shows the total period for which the P-bit in the flash
memory control register (FLMCR1) is set. It does not include the programming
verification time.)
*3 Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
*4 Maximum programming time (tP (max) = wait time after P-bit setting (z) × maximum
programming count (N))
*5 Number of times when the wait time after P-bit setting (z) = 200 µs.
The number of writes should be set according to the actual set value of z to allow
programming within the maximum programming time (tP).
*6 Maximum erase time (tE (max) = Wait time after E-bit setting (z) × maximum erase
count (N))
*7 Number of times when the wait time after E-bit setting (z) = 10 ms.
The number of erases should be set according to the actual set value of z to allow
erasing within the maximum erase time (tE).