Product data
2
• Wait function in slave mode (I
2
C bus format)
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
Data transfer end (including transmission mode transition with I
2
C bus format and address
reception after loss of master arbitration)
Address match: when any slave address matches or the general call address is received in
slave receive mode (I
2
C bus format)
Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pins)
Two pins—P52/SCL0 and P47/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
Two pins—P24/SCL1 and P23/SDA1—(normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
• Automatic switching from formatless mode to I
2
C bus format (channel 0 only)
Slave mode addressless (no start condition/end condition, non-addressing) operation
Operation using common data pin (SDA) and independent clock pin (VSYNCI, SCL) pin
configuration
Automatic switching from formatless mode to I
2
C bus format on fall of SCL
16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the I
2
C bus interface.
Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and
channel 1 I/O pins differ in structure, and have different specifications for permissible applied
voltages. For details, see section 22, Electrical Characteristics.