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Hitachi 16-Bit Single-Chip Microcomputer H8S/2128 Series, H8S/2124 Series H8S/2128F-ZTAT™ Hardware Manual — Supplement — ADE-602-114B Rev. 3.0 5/22/02 Hitachi, Ltd.
Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice.
February 2002 Announcement of Changes to Hardware Manual Contents This is to announce that, with the addition of H8S/2128S and H8S/2127S products, a Supplement has been prepared for the following sections of the Hitachi single-chip microcomputer H8S/2128 Series and H8S/2124 Series Hardware Manual.
Contents Section 16 I2 C Bus Interface [Option]............................................................................ 16.1 Overview ............................................................................................................................ 16.1.1 Features ................................................................................................................. 16.1.2 Block Diagram ..................................................................................................
22.3 Electrical Characteristics [H8S/2128S Series] ................................................................... 22.3.1 Absolute Maximum Ratings.................................................................................. 22.3.2 DC Characteristics ................................................................................................ 22.3.3 AC Characteristics ................................................................................................ 22.3.
Section 16 I2C Bus Interface [Option] A two-channel I2C bus interface is available as an option in the H8S/2128 Series. The I2C bus interface is not available for the H8S/2124 Series. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432127SWFA 2. The product number is identical for F-ZTAT versions.
• Wait function in slave mode (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible.
Formatless dedicated clock (channel 0 only) ø PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Second slave address register PS: Prescaler Interrupt generator Interrup
Vcc VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in This chip SCL out SCL out SDA in SDA in SDA out SDA out SCL SDA SDA in SCL SDA SCL out SCL in (Slave 1) (Slave 2) Figure 16.2 I2C Bus Interface Connections (Example: This Chip as Master) 16.1.3 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I2C bus interface. Table 16.
16.1.4 Register Configuration Table 16.2 summarizes the registers of the I2C bus interface. Table 16.
16.2 Register Descriptions 16.2.
ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started (Initial value) [Clearing conditions] • • • • When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) When a stop condition is detected in the bus line state after a stop condition is issued with the I 2C bus format or serial format selected When a stop condition is detected with the I 2C bus format selected In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after receptio
16.2.2 Slave Address Register (SAR) Bit 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format.
DDCSWR Bit 6 SAR Bit 0 SARX Bit 0 SW FS FSX Operating Mode 0 0 0 I 2C bus format • I 2C bus format 1 1 (Initial value) • SAR slave address recognized • SARX slave address ignored I 2C bus format 0 1 • SAR slave address ignored • SARX slave address recognized Synchronous serial format • 1 SAR and SARX slave addresses recognized SAR and SARX slave addresses ignored 0 0 Formatless mode (start/stop conditions not detected) 0 1 • 1 0 1 1 Acknowledge bit used Formatless mo
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format. • I2C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only • Formatless mode: non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode.
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I2C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred.
Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate.
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I 2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low.
Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to 0, the I2C bus interface module is halted and its internal states are cleared. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1.
Bit 5 Bit 4 MST TRS Operating Mode 0 0 Slave receive mode 1 Slave transmit mode 0 Master receive mode 1 Master transmit mode 1 (Initial value) Bit 5 MST Description 0 Slave mode (Initial value) [Clearing conditions] 1. When 0 is written by software 2. When bus arbitration is lost after transmission is started in I 2C bus format master mode 1 Master mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing condition 2) 2.
Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. In the H8S/2128 Series, the DTC can be used to perform continuous transfer.
Bit 2 BBSY Description 0 Bus is free (Initial value) [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected Bit 1—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has issued an interrupt request to the CPU.
Bit 1 IRIC Description 0 Waiting for transfer, or transfer in progress 1 [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) Interrupt requested (Initial value) [Setting conditions] • I 2C bus format master mode 1.
When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored.
Bit 7 ESTP Description 0 No error stop condition (Initial value) [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2.
Bit 5 IRTR Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRTR after reading IRTR = 1 2.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL Description 0 Bus arbitration won (Initial value) [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] 1.
Bit 1—General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ Description 0 General call address not recognized (Initial value) [Clearing conditions] 1.
16.2.7 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 — IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the I2C interface operating mode (when the on-chip IIC option is included), and on-chip flash memory (F-ZTAT versions), and selects the TCNT input clock source.
16.2.8 DDC Switch Register (DDCSWR) Bit 7 6 5 4 3 2 1 0 SWE SW IE IF CLR3 CLR2 CLR1 CLR0 Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/(W)*1 W*2 W*2 W*2 W*2 Notes: *1 Only 0 can be written, to clear the flag. *2 Always read as 1. DDCSWR is an 8-bit readable/writable register that is used to initialize IIC and controls IIC internal latch clearance. DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bits 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when automatic format switching is executed for IIC channel 0. Bit 5 IE Description 0 Interrupt when automatic format switching is executed is disabled 1 Interrupt when automatic format switching is executed is enabled (Initial value) Bits 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the CPU when automatic format switching is executed for IIC channel 0.
Bit 3 Bit 2 Bit 1 Bit 0 CLR3 CLR2 CLR1 CLR0 Description 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 0 IIC1 internal latch cleared 1 IIC0 and IIC1 internal latches cleared — Invalid setting 1 1 — 16.2.
MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode. MSTPCRL Bit 3 MSTP3 Description 0 IIC channel 1 module stop mode is cleared 1 IIC channel 1 module stop mode is set 16.3 Operation 16.3.1 I2C Bus Data Format (Initial value) The I2C bus interface has serial and I2C bus formats. The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures 16.3 (a) and (b). The first frame following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0 or FSX = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) m (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 ≥ 1) Figure 16.
Table 16.4 I2C Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address, by which the master device selects a slave device R/W Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 A Acknowledge.
The master device sequentially sends the transmit clock and the data written to ICDR with the timing shown in figure 16.7. The selected slave device (i.e. , the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. (7) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse.
Start condition generation SCL (master output) 1 SDA (master output) bit 7 2 bit 6 3 bit 5 4 bit 4 5 bit 3 6 bit 2 Slave address SDA (slave output) 7 bit 1 8 1 9 bit 7 bit 0 R/W 2 [7] bit 6 Data 1 A [5] IRIC IRTR ICDR address + R/W Note: Data write timing in ICDR ICDR Writing prohibited Data 1 ICDR Writing enable User processing [4] Write BBSY = 1 and SCP = 0 (start condition issuance) [6] ICDR write [6] IRIC clear [9] ICDR write [9] IRIC clear Figure 16.
(3) The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. If the first frame is the final reception frame, execute the end processing as described in (l0). (4) Clear the IRIC flag to 0 to release from the wait state.
Master transmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 SDA (slave output) A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data 1 9 [3] 1 2 Bit7 Bit6 4 5 Bit5 Bit4 Bit3 Data 2 [5] SDA (master output) 3 A IRIC IRTR ICDR Data 1 [2] IRIC clear [1] TRS cleared to 0 [2] ICDR read (dummy read) WAIT set to 1 ACKB cleared to 0 User processing [4] IRIC clear [6] ICDR read (Data 1) [7] IRIC clear Figure 16.
16.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. [2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1.
Start condition generation SCL (master output) 1 2 3 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 9 1 2 Bit 7 Bit 6 SCL (slave output) SDA (master output) Slave address SDA (slave output) Bit 1 Bit 0 R/W Data 1 [4] A RDRF IRIC Interrupt request generation ICDRS Address + R/W ICDRR User processing Address + R/W [5] ICDR read [5] IRIC clear Figure 16.
SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 3 4 5 6 7 8 9 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCL (slave output) SDA (master output) Data 1 SDA (slave output) Bit 7 Bit 6 [4] Data 2 A [4] A RDRF Interrupt request generation Interrupt request generation IRIC ICDRS Data 1 ICDRR Data 1 User processing [5] ICDR read Data 2 Data 2 [5] IRIC clear Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) 16.3.
flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 16.11. [4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse.
16.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 16.12 shows the IRIC set timing and SCL control.
16.3.7 Automatic Switching from Formatless Mode to I2C Bus Format Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating mode. Switching from formatless mode to the I2C bus format (slave mode) is performed automatically when a falling edge is detected on the SCL pin.
16.3.8 Operation Using the DTC The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.5 shows some examples of processing using the DTC.
16.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Start [1] Initialize Initialize [2] Test the status of the SCL and SDA lines. Read BBSY in ICCR No BBSY = 0? Yes [3] Select master transmit mode. Set MST = 1 and TRS = 1 in ICCR [4] Start condition issuance Write BBSY = 1 and SCP = 0 in ICCR [5] Wait for a start condition generation Read IRIC in ICCR No IRIC = 1? Yes [6] Set transmit data for the first byte (slave address + R/W).
Master receive operation Set TRS = 0 in ICCR [1] Select receive mode Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. Read ICDR Clear IRIC in ICCR [3] Wait for 1 byte to be received. (8th clock falling edge) Read IRIC in ICCR No IRIC = 1? Yes Last receive ? Yes No No Clear IRIC in ICCR [4] Clear IRIC to trigger the 9th clock.
Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR [2] No IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). Clear IRIC in ICCR [3] Start receiving. The first read is a dummy read.
Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR [1] [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Clear IRIC in ICCR [3] Test for end of transfer. [4] Select slave receive mode. Read IRIC in ICCR No [2] [5] Dummy read (to release the SCL line). IRIC = 1? Yes Read ACKB in ICSR No [3] End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR [4] Read ICDR [5] Clear IRIC in ICCR End Figure 16.
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.
16.4 Usage Notes • In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0.
• The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line.
Table 16.8 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item t SCLHO t SCLLO t BUFO t STAHO t STASO tcyc Indication 0.5tSCLO (–tSr) ø= 8 MHz ø= ø= ø= 10 MHz 16 MHz 20 MHz –1000 4000 4000 4000 4000 4000 4000 High-speed –300 mode 600 950 950 950 950 950 Standard mode –250 4700 4750 4750 4750 4750 4750 High-speed –250 mode 1300 1000* 1 1000* 1 1000* 1 1000* 1 1000* 1 0.
Time Indication (at Maximum Transfer Rate) [ns] Item tcyc Indication t SDAHO 3t cyc I 2C Bus SpecifitSr/tSf Influence cation ø = (Min.) 5 MHz (Max.) ø= 8 MHz ø= ø= ø= 10 MHz 16 MHz 20 MHz 0 0 600 375 300 188 150 High-speed 0 mode 0 600 375 300 188 150 Standard mode Notes: *1 Does not meet the I 2C bus interface specification.
Stop condition Start condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR reading prohibited Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 16.
[1] Wait for end of 1-byte transfer. IRIC= 1 ? No [1] [2] Determine whether SCL is low. Yes Clear IRIC in ICSR Start condition issuance? [3] Issue restart condition instruction for retransmission. [4] Determine whether start condition is generated or not. No Other processing [5] Set transmit data (slave address + R/W). Yes SCL= Low ? Note: Program so that processing from [3] to [5] is executed continuously.
• Notes on I 2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising of the 9th SCL clock, issue the stop condition instruction after reading SCL and determining it to be low, as shown below.
Section 22 Electrical Characteristics 22.1 Voltage of Power Supply and Operating Range The power supply voltage and operating range (shaded part) for each product are shown in table 22.1. Table 22.1 Power Supply Voltage and Operating Range (1) Product/ Power supply HD64F2128 Product/ Power supply 5 V version VCC HD64F2128V 5.5 V Flash Memory Programming 4.5 V 2 MHz 3 V version VCC Select 5.0 V ± 0.5 V for programming condition in PROM programmer 5.5 V Select 5.0 V ± 0.
Table 22.1 Power Supply Voltage and Operating Range (2) Product/ Power supply 5 V version 4 V version HD6432128S VCC VCC HD6432128SW 5.5 V 5.5 V HD6432127S (Mask ROM Products) 3 V version VCC 4.5 V HD6432127SW 4.0 V 3.6 V 2.7 V 2 MHz 20 MHz 2 MHz fop 2 MHz 10 MHz fop 16 MHz fop VCC1 pin V CC = 5.0 V ± 10% V CC = 4.0 V to 5.5 V V CC = 2.7 V to 3.6 V (When using CIN input, VCC = 3.0 V to 3.6 V) VCL pin V CL = C connection V CL = C connection V CL = V CC connection AVCC = 5.
22.2 Electrical Characteristics [H8S/2128 Series, H8S/2128 F-ZTAT] 22.2.1 Absolute Maximum Ratings Table 22.2 lists the absolute maximum ratings. Table 22.2 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +7.0 V Input voltage (except ports 6, and 7) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.3 V Input voltage (CIN input selected for port 6) Vin Lower voltage of –0.3 to V CC +0.3 and AVCC +0.
22.2.2 DC Characteristics Table 22.3 lists the DC characteristics. Table 22.4 lists the permissible output currents. Table 22.3 DC Characteristics (1) Conditions: VCC = 5.0 V ± 10%, AVCC*1 = 5.0 V ± 10%, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*8 (regular specifications), Ta = –40 to +85°C*8 (wide-range specifications) Item Symbol Min Typ Max Unit 1.0 — — V — — VCC × 0.7 V 0.4 — — V VCC – 0.7 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 2.0 — AVCC +0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V –I P 50 — 300 µA Vin = 0 V Cin — — 80 pF NMI — — 50 pF Vin = 0 V f = 1 MHz Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 70 90 mA f = 20 MHz — 55 75 mA f = 20 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.5 3.0 mA — 0.01 5.0 µA AVCC = 2.0 V to 5.5 V 4.5 — 5.
*5 The upper limit of the port 6 applied voltage is V CC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for V IH min = VCC – 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. *7 The values are for VRAM ≤ VCC < 4.5 V, VIH min = VCC × 0.9, and V IL max = 0.3 V.
Table 22.3 DC Characteristics (2) Conditions: VCC = 4.0 V to 5.5 V*8, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*8 (regular specifications), Ta = –40 to +85°C*8 (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions 1.0 — — V — — VCC × 0.7 V VCC = 4.5 V to 5.5 V 0.4 — — V 0.8 — — V — — VCC × 0.7 V 0.3 — — VCC – 0.7 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 2.0 — AVCC +0.3 V Input pins except (1) and (2) above 2.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Input pull-up MOS current –I P 50 — 300 µA Vin = 0 V, VCC = 4.5 V to 5.5 V 30 — 200 µA Vin = 0 V, VCC < 4.5 V — — 80 pF NMI — — 50 pF Vin = 0 V, f = 1 MHz, Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 55 75 mA f = 16 MHz — 42 62 mA f = 16 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.
*6 Current dissipation values are for V IH min = VCC – 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. *7 The values are for VRAM ≤ VCC < 4.0 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. *8 For flash memory program/erase operations, the applicable ranges are VCC = 4.5 V to 5.5 V and T a = 0 to +75°C (regular specifications) or T a = 0 to +85°C (wide-range specifications).
Table 22.3 DC Characteristics (3) Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (Flash memory version): Item VCC = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*8 Symbol 2 Schmitt P67 to P60 * * , (1) trigger input IRQ2 to IRQ0* 3 voltage VT – VT + RES, STBY, (2) NMI, MD1, MD0 VIH Input high voltage Input low voltage 5 Typ Max Unit VCC × 0.2 — — V — VCC × 0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V –I P 10 — 150 µA Vin = 0 V, VCC = 2.7 V to 3.6 V Cin — — 80 pF NMI — — 50 pF Vin = 0 V, f = 1 MHz, Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 40 52 mA f = 10 MHz — 30 42 mA f = 10 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.5 3.0 mA — 0.01 5.0 µA AVCC = 2.
*5 The upper limit of the port 6 applied voltage is V CC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for V IH min = VCC – 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. *7 The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC × 0.9, and V IL max = 0.3 V.
Table 22.4 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
Table 22.5 Bus Drive Characteristics Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT – VT+ + VT – VT – Min Typ Max Unit Test Conditions VCC × 0.3 — — V VCC = 2.7 V to 5.5 V — — VCC × 0.7 VCC = 2.7 V to 5.5 V VCC × 0.05 — — VCC = 2.7 V to 5.5 V Input high voltage VIH VCC × 0.7 — VCC + 0.5 Input low voltage VIL –0.5 — VCC × 0.3 Output low voltage VOL — — 0.
This chip 600 Ω Ports 1 to 3 LED Figure 22.2 LED Drive Circuit (Example) 22.2.3 AC Characteristics Figure 22.3 shows the test conditions for the AC characteristics. VCC RL Chip output pin C RH C = 30 pF: All ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V Figure 22.
(1) Clock Timing Table 22.6 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 20, Clock Pulse Generator. Table 22.6 Clock Timing Condition A: VCC = 5.
tcyc tCH tCf ø tCL tCr Figure 22.4 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES ø Figure 22.5 Oscillation Settling Timing ø NMI IRQi (i = 0, 1, 2) tOSC2 Figure 22.
(2) Control Signal Timing Table 22.7 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, and IRQ2. Table 22.7 Control Signal Timing Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, ø = 32.
ø tRESS tRESS RES tRESW Figure 22.7 Reset Input Timing ø tNMIH tNMIS NMI tNMIW IRQi (i = 2 to 0) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22.
(3) Bus Timing Table 22.8 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 22.8 Bus Timing Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data t ACC3 access time 3 — 2.0 × t cyc – 30 — 2.0 × t cyc – 40 — 2.0 × t cyc – 60 ns Read data t ACC4 access time 4 — 2.5 × t cyc – 25 — 2.5 × t cyc – 35 — 2.5 × t cyc – 50 ns Read data t ACC5 access time 5 — 3.0 × t cyc – 30 — 3.0 × t cyc – 40 — 3.
T1 T2 ø tAD A15 to A0, IOS* tCSD tAS tAH tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D7 to D0 (read) tWRD2 WR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 T3 ø tAD A15 to A0, IOS* tCSD tAS tASD tASD tAH AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D7 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 TW T3 ø A15 to A0, IOS* AS* RD (read) D7 to D0 (read) WR (write) D7 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 or T3 T1 T2 ø tAD A15 to A0, IOS* tAS tASD tAH tASD AS* tRSD2 RD (read) tACC3 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 or T3 T1 ø tAD A15 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
(4) Timing of On-Chip Supporting Modules Tables 22.9 and 22.10 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, and IRQ2), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 22.9 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 32.
Condition A Condition B Condition C 20 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions t TMOD — 50 — 50 — 100 ns Timer reset input t TMRS setup time 30 — 30 — 50 — Figure 22.19 Timer clock input t TMCS setup time 30 — 30 — 50 — Figure 22.18 Timer clock pulse width Item TMR 16 MHz Timer output delay time Single edge t TMCWH 1.5 — 1.5 — 1.5 — Both edges t TMCWL 2.5 — 2.5 — 2.5 — t PWOD — 50 — 50 — 100 ns Figure 22.
T1 T2 ø tPRS tPRH Ports 1 to 7 (read) tPWD Ports 1 to 6 (write) Figure 22.14 I/O Port Input/Output Timing ø tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 22.15 FRT Input/Output Timing ø tFTCS FTCI tFTCWL tFTCWH Figure 22.
ø tTMOD TMO0, TMO1 TMOX Figure 22.17 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH Figure 22.18 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 22.19 8-Bit Timer Reset Input Timing ø tPWOD PW15 to PW0, PWX1, PWX0 Figure 22.
tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 22.21 SCK Clock Input Timing SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 22.22 SCI Input/Output Timing (Synchronous Mode) ø tTRGS ADTRG Figure 22.
Table 22.10 I2C Bus Timing Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, ø = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Item Symbol Min Typ Max Unit SCL clock cycle time t SCL 12 — — t cyc SCL clock high pulse width t SCLH 3 — — t cyc SCL clock low pulse width t SCLL 5 — — t cyc SCL, SDA input rise time t Sr — — 7.
VIH SDA0, SDA1 VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0, SCL1 P* S* tSf Sr* tSCLL tSDAS tSr tSCL P* tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 22.
22.2.4 A/D Conversion Characteristics Tables 22.11 and 22.12 list the A/D conversion characteristics. Table 22.11 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10% VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Table 22.12 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10% VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
22.2.5 Flash Memory Characteristics Table 22.13 shows the flash memory characteristics. Table 22.13 Flash Memory Characteristics Conditions (5 V version): VCC = 5.0 V ± 10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications) Conditions for low-voltage version:VCC = 3.0 V to 3.
Item Erase Symbol Min Typ Max Unit Wait time after SWE-bit setting* 1 x 10 — — µs Wait time after ESU-bit setting* 1 y 200 — — µs Wait time after E-bit setting * 1 *6 z 5 — 10 ms Wait time after E-bit clear*1 α 10 — — µs Wait time after ESU-bit clear* 1 β 10 — — µs Wait time after EV-bit setting * 1 γ 20 — — µs Wait time after dummy write* 1 ε 2 — — µs Wait time after EV-bit clear * 1 η 5 — — µs Maximum erase count* 1 *6 *7 N — — 120 Times Test Con
22.2.6 Usage Note The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc.
22.3 Electrical Characteristics [H8S/2128S Series] 22.3.1 Absolute Maximum Ratings Table 22.14 lists the absolute maximum ratings. Table 22.14 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage * 1 VCC –0.3 to +7.0 V Power supply voltage * (3 V version) 1 VCC –0.3 to +4.3 V Power supply voltage * 2 (VCL version) VCL –0.3 to +4.3 V Input voltage (except ports 6, 7) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.
22.3.2 DC Characteristics Table 22.15 lists the DC characteristics. Table 22.16 lists the permissible output currents. Table 22.15 DC Characteristics (1) Conditions: VCC = 5.0 V ± 10%, AVCC*1 = 5.0 V ± 10%, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Schmitt P67 to P60 * 2 * 5, (1) VT– 1.0 3 8 trigger input IRQ2 to IRQ0* * + VT — voltage + – VT – VT 0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V –I P 30 — 300 µA Vin = 0 V Cin — — 80 pF NMI — — 50 pF Vin = 0 V f = 1 MHz Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 45 55 mA f = 20 MHz — 30 41 mA f = 20 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.5 3.0 mA — 0.01 5.0 µA AVCC = 2.0 V to 5.5 V 4.5 — 5.
*5 The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for V IH min = VCC – 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. *7 The values are for VRAM ≤ VCC < 4.5 V, VIH min = VCC – 0.2 V, and VIL max = 0.2 V.
Table 22.15 DC Characteristics (2) Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions — — V — VCC × 0.7 V VCC = 4.5 V to 5.5 V — — V 0.8 — — V — — VCC × 0.7 V 0.3 — — Schmitt P67 to P60 * 2 * 5, (1) VT– 1.0 3 8 trigger input IRQ2 to IRQ0* * + VT — voltage + – VT – VT 0.
Item Input leakage current Symbol Min Typ Max Unit Test Conditions Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC – 0.5 V RES Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Input pull-up MOS current –I P 30 — 300 µA Vin = 0 V, VCC = 4.5 V to 5.5 V 20 — 200 µA Vin = 0 V, VCC < 4.
*5 *6 *7 *8 An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). In the H8S/2128S Series, P52/SCK0 and P47 (ICE = 0) high levels are driven by NMOS. The upper limit of the port 6 applied voltage is V CC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. Current dissipation values are for V IH min = VCC – 0.
Table 22.15 DC Characteristics (3) Conditions (Mask ROM version): VCC = 2.7 V to 3.6 V, AVCC*1 = 2.7 V to 3.6 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C Item Symbol Min Typ Max Unit — V Schmitt P67 to P60 * 2 * 5, (1) VT– VCC × 0.2 — 3 8 * * trigger input IRQ2 to IRQ0 + VT — — voltage + – VT – VT VCC × 0.05 — VCC × 0.7 V VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 VCC × 0.7 — AVCC +0.3 Input pins except (1) and (2) above VCC × 0.7 — VCC +0.3 V –0.3 — VCC × 0.1 V –0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V –I P 5 — 150 µA Vin = 0 V, VCC = 2.7 V to 3.6 V Cin — — 80 pF NMI — — 50 pF Vin = 0 V, f = 1 MHz, Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 24 30 mA f = 10 MHz — 15 23 mA f = 10 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.5 3.0 mA — 0.01 5.0 µA AVCC = 2.
*5 The upper limit of the port 6 applied voltage is V CC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for V IH min = VCC – 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. *7 The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC − 0.2 V, and VIL max = 0.2 V.
Table 22.16 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
Table 22.17 Bus Drive Characteristics Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 to 3.6 V (3 V version), VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol Min Typ Max Unit VT – VCC × 0.3 — — V VT + — — VCC × 0.7 Test Conditions Input high voltage VIH VCC × 0.7 — VCC + 0.5 Input low voltage VIL –0.5 — VCC × 0.3 Output low voltage VOL — — 0.8 — — 0.5 I OL = 8 mA — — 0.
This chip 600 Ω Ports 1 to 3 LED Figure 22.26 LED Drive Circuit (Example) 22.3.3 AC Characteristics Figure 22.3 shows the test conditions for the AC characteristics. VCC RL Chip output pin C RH C = 30 pF: All ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V Figure 22.
(1) Clock Timing Table 22.18 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 20, Clock Pulse Generator. Table 22.18 Clock Timing Condition A: VCC = 5.
tcyc tCH tCf ø tCL tCr Figure 22.28 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES ø Figure 22.29 Oscillation Settling Timing ø NMI IRQi (i = 0, 1, 2) tOSC2 Figure 22.
(2) Control Signal Timing Table 22.19 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, and IRQ2. Table 22.19 Control Signal Timing Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, ø = 32.
ø tRESS tRESS RES tRESW Figure 22.31 Reset Input Timing ø tNMIH tNMIS NMI tNMIW IRQi (i = 2 to 0) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22.
(3) Bus Timing Table 22.20 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 22.20 Bus Timing Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data t ACC3 access time 3 — 2.0 × t cyc – 30 — 2.0 × t cyc – 40 — 2.0 × t cyc – 60 ns Read data t ACC4 access time 4 — 2.5 × t cyc – 25 — 2.5 × t cyc – 35 — 2.5 × t cyc – 50 ns Read data t ACC5 access time 5 — 3.0 × t cyc – 30 — 3.0 × t cyc – 40 — 3.
T1 T2 ø tAD A15 to A0, IOS* tCSD tAS tAH tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D7 to D0 (read) tWRD2 WR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 T3 ø tAD A15 to A0, IOS* tCSD tAS tASD tASD tAH AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D7 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 TW T3 ø A15 to A0, IOS* AS* RD (read) D7 to D0 (read) WR (write) D7 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 or T3 T1 T2 ø tAD A15 to A0, IOS* tAS tASD tAH tASD AS* tRSD2 RD (read) tACC3 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 or T3 T1 ø tAD A15 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
(4) Timing of On-Chip Supporting Modules Tables 22.21 and 22.22 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, and IRQ2), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 22.21 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 32.
Condition A Condition B Condition C 20 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions t TMOD — 50 — 50 — 100 ns Timer reset input t TMRS setup time 30 — 30 — 50 — Figure 22.43 Timer clock input t TMCS setup time 30 — 30 — 50 — Figure 22.42 Timer clock pulse width Item TMR 16 MHz Timer output delay time Single edge t TMCWH 1.5 — 1.5 — 1.5 — Both edges t TMCWL 2.5 — 2.5 — 2.5 — t PWOD — 50 — 50 — 100 ns Figure 22.
T1 T2 ø tPRS tPRH Ports 1 to 7 (read) tPWD Ports 1 to 6 (write) Figure 22.38 I/O Port Input/Output Timing ø tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 22.39 FRT Input/Output Timing ø tFTCS FTCI tFTCWL tFTCWH Figure 22.
ø tTMOD TMO0, TMO1 TMOX Figure 22.41 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH Figure 22.42 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 22.43 8-Bit Timer Reset Input Timing ø tPWOD PW15 to PW0, PWX1, PWX0 Figure 22.
tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 22.45 SCK Clock Input Timing SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 22.46 SCI Input/Output Timing (Synchronous Mode) ø tTRGS ADTRG Figure 22.
Table 22.22 I2C Bus Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V, ø = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Item Symbol Min Typ Max Unit SCL clock cycle time t SCL 12 — — t cyc SCL clock high pulse width t SCLH 3 — — t cyc SCL clock low pulse width t SCLL 5 — — t cyc SCL, SDA input rise time t Sr — — 7.
VIH SDA0, SDA1 VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0, SCL1 P* S* tSf Sr* tSCLL tSDAS tSr tSCL P* tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 22.
22.3.4 A/D Conversion Characteristics Tables 22.23 and 22.24 list the A/D conversion characteristics. Table 22.23 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10% VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Table 22.24 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10% VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
22.3.5 Usage Note (1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc.
(3) Specification differences in internal I/O registers Mask ROM version of H8S/2128S, H8S/2127S are different from the H8S/2128 Series and H8S/2124 Series in the specification of control registers for peripheral functions.
22.4 Electrical Characteristics [H8S/2124 Series] 22.4.1 Absolute Maximum Ratings Table 22.25 lists the absolute maximum ratings. Table 22.25 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +7.0 V Input voltage (except ports 6, and 7) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.3 V Input voltage (CIN input selected for port 6) Vin Lower voltage of –0.3 to V CC +0.3 and AVCC +0.
22.4.2 DC Characteristics Table 22.26 lists the DC characteristics. Table 22.27 lists the permissible output currents. Table 22.26 DC Characteristics (1) Conditions: VCC = 5.0 V ± 10%, AVCC*1 = 5.0 V ± 10%, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit 1.0 — — V — — VCC × 0.7 V 0.4 — — V VCC – 0.7 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 2.0 — AVCC +0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V –I P 50 — 300 µA Vin = 0 V Cin — — 80 pF NMI — — 50 pF Vin = 0 V f = 1 MHz Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 70 90 mA f = 20 MHz — 55 75 mA f = 20 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.5 3.0 mA — 0.01 5.0 µA AVCC = 2.0 V to 5.5 V 4.5 — 5.
Table 22.26 DC Characteristics (2) Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions 1.0 — — V — — VCC × 0.7 V VCC = 4.5 V to 5.5 V 0.4 — — V 0.8 — — V — — VCC × 0.7 V 0.3 — — VCC – 0.7 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 2.0 — AVCC +0.3 V Input pins except (1) and (2) above 2.0 — VCC +0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Input pull-up MOS current –I P 50 — 300 µA Vin = 0 V, VCC = 4.5 V to 5.5 V 30 — 200 µA Vin = 0 V, VCC < 4.5 V — — 80 pF NMI — — 50 pF Vin = 0 V, f = 1 MHz, Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 55 75 mA f = 16 MHz — 42 62 mA f = 16 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.
Table 22.26 DC Characteristics (3) Conditions : VCC = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C Item Symbol 2 Schmitt P67 to P60 * * , (1) trigger input IRQ2 to IRQ0* 3 voltage VT – VT + RES, STBY, (2) NMI, MD1, MD0 VIH Input high voltage Input low voltage 4 Min Typ Max Unit VCC × 0.2 — — V — VCC × 0.7 V — Test Conditions VCC × 0.05 — — VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 VCC × 0.7 — AVCC +0.
Item Symbol Min Typ Max Unit Test Conditions Three-state Ports 1 to 6 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V –I P 10 — 150 µA Vin = 0 V, VCC = 2.7 V to 3.6 V Cin — — 80 pF NMI — — 50 pF Vin = 0 V, f = 1 MHz, Ta = 25°C P52, P47, P24, P23 — — 20 pF Input pins except (4) above — — 15 pF — 40 52 mA f = 10 MHz — 30 42 mA f = 10 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.5 3.0 mA — 0.01 5.0 µA AVCC = 2.
Table 22.27 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
This chip 2 kΩ Port Darlington pair Figure 22.50 Darlington Pair Drive Circuit (Example) This chip 600 Ω Ports 1 to 3 LED Figure 22.51 LED Drive Circuit (Example) 22.4.3 AC Characteristics Figure 22.52 shows the test conditions for the AC characteristics. VCC RL Chip output pin C RH Figure 22.52 Output Load Circuit 138 C = 30 pF: All ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.
(1) Clock Timing Table 22.28 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 20, Clock Pulse Generator. Table 22.28 Clock Timing Condition A: VCC = 5.
tcyc tCH tCf ø tCL tCr Figure 22.53 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES ø Figure 22.54 Oscillation Settling Timing ø NMI IRQi (i = 0, 1, 2) tOSC2 Figure 22.
(2) Control Signal Timing Table 22.29 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, and IRQ2. Table 22.29 Control Signal Timing Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, ø = 32.
ø tRESS tRESS RES tRESW Figure 22.56 Reset Input Timing ø tNMIH tNMIS NMI tNMIW IRQi (i = 2 to 0) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22.
(3) Bus Timing Table 22.30 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 22.30 Bus Timing Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data t ACC3 access time 3 — 2.0 × t cyc – 30 — 2.0 × t cyc – 40 — 2.0 × t cyc – 60 ns Read data t ACC4 access time 4 — 2.5 × t cyc – 25 — 2.5 × t cyc – 35 — 2.5 × t cyc – 50 ns Read data t ACC5 access time 5 — 3.0 × t cyc – 30 — 3.0 × t cyc – 40 — 3.
T1 T2 ø tAD A15 to A0, IOS* tCSD tAS tAH tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D7 to D0 (read) tWRD2 WR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 T3 ø tAD A15 to A0, IOS* tCSD tAS tASD tASD tAH AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D7 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 TW T3 ø A15 to A0, IOS* AS* RD (read) D7 to D0 (read) WR (write) D7 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 or T3 T1 T2 ø tAD A15 to A0, IOS* tAS tASD tAH tASD AS* tRSD2 RD (read) tACC3 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
T1 T2 or T3 T1 ø tAD A15 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.
(4) Timing of On-Chip Supporting Modules Table 22.31 shows the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, and IRQ2), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 22.31 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ± 10%, VSS = 0 V, ø = 32.
Condition A Condition B Condition C 20 MHz SCI A/D converter 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Timer output delay time t TMOD — 50 — 50 — 100 ns Timer reset input setup time t TMRS 30 — 30 — 50 — Figure 22.68 Timer clock input setup time t TMCS 30 — 30 — 50 — Figure 22.67 Timer clock pulse width Single edge t TMCWH 1.5 — 1.5 — 1.5 — Both edges t TMCWL 2.5 — 2.5 — 2.
T1 T2 ø tPRS tPRH Ports 1 to 7 (read) tPWD Ports 1 to 6 (write) Figure 22.63 I/O Port Input/Output Timing ø tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 22.64 FRT Input/Output Timing ø tFTCS FTCI tFTCWL tFTCWH Figure 22.
ø tTMOD TMO0, TMO1 Figure 22.66 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1, TMIY tTMCWL tTMCWH Figure 22.67 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1, TMIY Figure 22.68 8-Bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 22.
SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 22.70 SCI Input/Output Timing (Synchronous Mode) ø tTRGS ADTRG Figure 22.
22.4.4 A/D Conversion Characteristics Tables 22.32 and 22.33 list the A/D conversion characteristics. Table 22.32 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10% VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Table 22.33 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10% VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
22.4.5 Usage Note The specifications of the H8S/2128 F-ZTAT version and H8S/2124 Series mask ROM version differ in terms of on-chip module functions provided and port (P47, P52) output specifications. Also, while the F-ZTAT and mask ROM versions both satisfy the electrical characteristics shown in this manual, actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, etc.
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Appendix F Product Code Lineup Table F.
Product Type H8S/2128S H8S/2128S Mask ROM Standard product Series version (5 V version, 4 V version) Package (Hitachi Package Code) Product Code Mark Code HD6432128S HD6432128S(***)PS 64-pin shrink DIP (DP-64S) HD6432128S(***)FA 64-pin QFP (FP-64A) HD6432128S(***)TF 80-pin TQFP (TFP-80C) HD6432128SV(***)PS 64-pin shrink DIP (DP-64S) HD6432128SV(***)FA 64-pin QFP (FP-64A) HD6432128SV(***)TF 80-pin TQFP (TFP-80C) Low-voltage version HD6432128SV (3 V version) Notes Under planning Standard p
Product Type H8S/2124 Series H8S/2122 H8S/2120 Mask ROM Standard product version (5 V version, 4 V version, 3 V version) Mask ROM Standard product version (5 V version, 4 V version, 3 V version) Package (Hitachi Package Code) Product Code Mark Code HD6432122 HD6432122(***)PS 64-pin shrink DIP (DP-64S) HD6432122(***)FA 64-pin QFP (FP-64A) HD6432122(***)TF 80-pin TQFP (TFP-80C) HD6432120(***)PS 64-pin shrink DIP (DP-64S) HD6432120(***)FA 64-pin QFP (FP-64A) HD6432120(***)TF 80-pin TQFP (TF
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H8S/2128 Series, H8S/2124 Series, H8S/2128F-ZTAT™ Hardware Manual (Supplement) Publication Date: 1st Edition, December 1997 3rd Edition, May 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
