Technical information

8
Default:
Default:Default:
Default:
Figure 2.1 Default User System Interface Circuit
Mode Pins (MD1 and MD0) and NMI:
Mode Pins (MD1 and MD0) and NMI: Mode Pins (MD1 and MD0) and NMI:
Mode Pins (MD1 and MD0) and NMI: The NMI signal is input to the MCU through the
emulator control circuit. The rising/falling time of these signals must be 8 ns/V or less. The mode
pins are only monitored. The CPU mode depends on the HDI settings.
Figure 2.2 User System Interface Circuit for MD1, MD0, and NMI
RESET:
RESET:RESET:
RESET:
Figure 2.3 User System Interface Circuit for RESET