Technical data

FIRE Emulator for H8S and H8/300H 29 Exception Control

Exceptions during Break Mode

During break mode (application program not running), the hardware-caused exceptions are controlled by the

bondout CPU.

NMI

If a NMI occurs, then it is stored in the CPU. So, exception processing will occur after the first instruction of

the started emulation.

External level sensitive interrupts

If a level sensitive interrupt occurs, then it is not stored in the CPU. So, interrupt processing will not occur if

the /IRQ pin is not asserted until the emulation is started.

External edge sensitive interrupts

If an edge sensitive interrupt occurs, then it is stored in the CPU. So, interrupt processing will occur after the

first instruction of the started emulation.

Internal interrupts

If an internal interrupt occurs, then it is stored in the CPU. So, interrupt processing will occur after the first

instruction of the started emulation.