Technical data

FIRE Emulator for H8S and H8/300H 17 General SYStem Settings and Restrictions

SYStem.Option RAME Onchip RAM enable

This option must be set corresponding to the RAME bit in the SYSCR register of the cpu. The emulator

needs this information to set the breakpoints correctly.

SYStem.Option IMASKASM Mask interrupts during assembler step

If enabled, the interrupt mask bits of the cpu will be set during assembler single-step operations. The

interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are

restored to the value before the step.

SYStem.Option IMASKHLL Mask interrupts during HLL step

If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt

routine is not executed during single-step operations. After single step the interrupt mask bits are restored to

the value before the step.

Continue with CPU specific Special Settings and Restrictions

The following Special Settings and Restrictions are different for the used bondout chip.

• Special Settings and Restrictions of H8S/224x/23xx/265x

• Special Settings and Restrictions of H8S/21xx

• Special Settings and Restrictions of H8S/222x/223x/262x/263x

Format: SYStem.Option RAME [ON | OFF]

Format: SYStem.Option IMASKASM [ON | OFF]

Format: SYStem.Option IMASKHLL [ON | OFF]

NOTE: By changing the status register through target software, this option can affect

the flow of the target program. Accesses to the interrupt-mask bits will see the

wrong values.