Specifications

This model is incomplete and rather ad-hoc. For example, in the real processor the instruction
sequence
MOV.B #255, R3L
ADD.B R3L, R4H
has exactly the same effect on R4, Z and C as the single instruction ADD.B #255, R4H but in the
Bound-T model the instruction sequence results in opaque values for Z and C while the single
instruction sets Z and C to non-opaque values as shown above.
The following table shows how Bound-T models the flag setting by the H8/300 instructions
(roughly alphabetically ordered). The table applies to instructions that stand alone, it does not
apply when two 8-bit instructions are combined into a 16-bit operation as described in
section 5.3. The symbol "−" means that the flag is not changed (neither in the model nor in the
real processor). When a register (Rd or Rs) is used in the Z and C conditions the value of the
register before the instruction is meant, and likewise for the Z and C flags themselves. The
word "result" means the value computed by the instruction (eg. the value of Rd after the
instruction).
Table 10: Condition flag definitions
Instruction Z condition C condition
ADD.B #<k = 0 .. 127>, Rd
opaque opaque
ADD.B #<k = 128 .. 255>, Rd
Rd = 256 − k Rd < 256 − k
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDX
opaque opaque
ADDS
− −
AND
result = 0
−
ANDC #k, CCR
Z and (bit 2 of k ) C and (bit 0 of k)
BAND, BIAND, BILD, BIOR, BIXOR,
BLD, BOR, BXOR
−
opaque
BCLR, BNOT, BSET, BST
− −
BTST
opaque
−
Bcc
− −
CMP.B Rd, Rs
Rd = Rs Rd < Rs
DAA
opaque opaque
DAS
opaque
−
DEC Rd
Rd = 1
−
DIVXU
opaque opaque
EEPMOV
− −
INC Rd
Rd = 255
−
JMP, JSR
− −
LDC #k, CCR
bit 2 of k bit 0 of k
LDC Rs, CCR
opaque opaque
MOV, MOVFPE, MOVTPE result = 0
−
MULXU
− −
26 Supported H8/300 Features Bound-T for H8/300