Specifications

Program Counter and Condition Code Register
The 16-bit Program Counter (PC) register points to the next instruction. Instructions are 16 or
32 bits in length and always start at an even address.
The 8-bit Condition Code Register (CCR) contains the usual condition flags: Z = zero,
C = carry, N = negative, V = overflow, H = half-carry (for BCD arithmetic). The CCR also
contains the interrupt mask bit and two user-defined flag bits.
Stack Pointer
The Stack Pointer SP (R7) has all the functionality of a general register but is implicitly used by
the call and return instructions and interrupt handling. Parameters can be passed on the stack
and local variables can be held on the stack. The stack can be placed anywhere in the memory
space (except in ROM, of course).
The stack grows down in memory (a push decreases the SP). The stack is a "full" stack which
means that SP points to the topmost occupied stack location (as opposed to the first empty
location).
Typically, the caller pushes parameters on the stack before the call; the call instruction then
pushes the return address; and the callee pushes its local variables. Local variables and
parameters can then be accessed with a positive offset from SP (addressing mode register-
indirect with displacement).
The push and pop instructions operate on word (16-bit) data. The H8/300 manual [4] advises
that the stack pointer should always be altered in word units and thus SP should always have
an even value.
Memory addressing modes
Memory is addressed by octet but single instructions can access octets or 16-bit words. Words
are stored in big-endian form; the high octet is always at an even address and the low octet at
the next odd address.
The addressing modes (forms of instruction operands) include immediate, absolute address,
register and register indirect. The register-indirect mode can include a constant displacement
or auto-increment or auto-decrement. Branches and calls also support PC-relative and memory
indirect (vectored) operands.
The H8/300 architecture is not (visibly) pipelined. This means that jumps and branches take
effect immediately; there are no "delay slots" and jump or branch instructions.
4.2 Instruction timing in the H8/300
Execution time in H8/300 is counted in execution states; one execution state corresponds to
one clock period.
The execution time of an instruction depends on the type of the instruction and on the kind of
memory that the instruction accesses. The fastest instructions take two states; for example an
ADD.B or ADD.W executed from the on-chip memory. Complex instructions that access memory
may have execution times of 20 or more states, depending on the length of the instruction, the
addressing mode, the data width and the memory areas that are accessed.
Instruction timing is usually independent of the processed data (register or memory values).
The exception is the instruction EEPMOV that copies a block of data from one memory address
to another; here the execution time depends on the size of the block, which is given in a
register.
Bound-T for H8/300 H8/300 Timing Analysis 17