Hardware manual

Rev. 3.0, 09/98, page 87 of 361
Figure 6.1 shows a schematic diagram of port 1.
P1n
Hardware standby
Mode 3
Mode 1 or 2
RP1
Reset
Reset
Mode 1
Reset
WP1
WP1D
WP1P
R
RS
R
Q
Q
Q
D
D
D
P1n DR
P1n DDR
P1n PCR
C
C
C
*
RP1P
WP1P:
WP1D:
WP1:
RP1P :
RP1:
n = 0 to 7
Note: * Set-priority
Write Port 1 PCR
Write Port 1 DDR
Write Port 1
Read Port 1 PCR
Read Port 1
Internal data bus
Internal address bus
Figure 6.1 Port 1 Schematic Diagram