Hardware manual

Rev. 3.0, 09/98, page 85 of 361

Port 1 Data Register (P1DR)H'FFB2

Bit:76543210

Initial value:00000000

Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W

P1DR is an 8-bit register containing the data for pins P1

to P1

. When the CPU reads P1DR, for

output pins it reads the value in the P1DR latch, but for input pins, it obtains the logic level

directly from the pin, bypassing the P1DR latch.

Port 1 Input Pull-Up Control Register (P1PCR)H'FFAC

Bit:76543210

PCR P1

PCR

Initial value:00000000

Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W

P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If

a bit in P1DDR is cleared to “0” (designating input) and the corresponding bit in P1PCR is set to

“1,” the input pull-up transistor for that bit is turned on.

Mode 1: In mode 1 (expanded mode without on-chip ROM), port 1 is automatically used for

address output. The port 1 data direction register is unwritable. All bits in P1DDR are

automatically set to “1” and cannot be cleared to “0.”

Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 1 can be selected on a

pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to “0,”

or for address output if its data direction bit is set to “1.”

Mode 3: In the single-chip mode port 1 is a general-purpose input/output port.

Reset: A reset clears P1DDR, P1DR, and P1PCR to all “0,” placing all pins in the input state

with the pull-up transistors off. In mode 1, when the chip comes out of reset, P1DDR is set to all

“1.”

Hardware Standby Mode: All pins are placed in the high-impedance state with the pull-up

transistors off. P1DR and P1PCR are initialized to H'00. In modes 2 and 3, P1DDR is initialized

to H'00.

Software Standby Mode: In the software standby mode, P1DDR, P1DR, and P1PCR remain in

their previous state. Address output pins are Low. General-purpose output pins continue to output

the data in P1DR.