Hardware manual

Rev. 3.0, 09/98, page vi of viii
11.2 Register Descriptions ........................................................................................................ 230
11.2.1 A/D Data Registers (ADDR)

H'FFE0 to H'FFE6.............................................. 230
11.2.2 A/D Control/Status Register (ADCSR)

H'FFE8 ............................................... 230
11.2.3 A/D Control Register (ADCR)

H'FFEA............................................................ 233
11.3 Operation........................................................................................................................... 234
11.3.1 Single Mode (SCAN = 0)..................................................................................... 234
11.3.2 Scan Mode (SCAN = 1) ....................................................................................... 237
11.3.3 Input Sampling Time and A/D Conversion Time ................................................ 239
11.3.4 External Trigger Input Timing ............................................................................. 241
11.4 Interrupts ........................................................................................................................... 242
Section 12 D/A Converter
................................................................................................. 243
12.1 Overview........................................................................................................................... 243
12.1.1 Features ................................................................................................................ 243
12.1.2 Block Diagram ..................................................................................................... 244
12.1.3 Input and Output Pins........................................................................................... 245
12.1.4 Register Configuration......................................................................................... 245
12.2 Register Descriptions ........................................................................................................ 246
12.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) H'FFA8, H'FFA9 ..................... 246
12.2.2 D/A Control Register (DACR) H'FFAA.............................................................. 246
12.3 Operation........................................................................................................................... 248
Section 13 RAM
................................................................................................................... 249
13.1 Overview........................................................................................................................... 249
13.2 Block Diagram .................................................................................................................. 249
13.3 RAM Enable Bit (RAME) in System Control Register (SYSCR) .................................... 250
13.4 Operation........................................................................................................................... 250
13.4.1 Expanded Modes (Modes 1 and 2)....................................................................... 250
13.4.2 Single-Chip Mode (Mode 3) ................................................................................ 250
Section 14 ROM
................................................................................................................... 251
14.1 Overview........................................................................................................................... 251
14.1.1 Block Diagram ..................................................................................................... 252
14.2 PROM Mode (H8/338, H8/337)........................................................................................ 252
14.2.1 PROM Mode Setup.............................................................................................. 252
14.2.2 Socket Adapter Pin Assignments and Memory Map............................................ 253
14.3 Programming..................................................................................................................... 257
14.3.1 Writing and Verifying.......................................................................................... 257
14.3.2 Notes on Writing.................................................................................................. 261
14.3.3 Reliability of Written Data................................................................................... 262
14.3.4 Erasing of Data..................................................................................................... 263
14.4 Handling of Windowed Packages ..................................................................................... 263