Hardware manual

Rev. 3.0, 09/98, page 75 of 361
4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
Contention between Interrupt Request and Disable: When software clears the enable bit of an
interrupt to “0” to disable the interrupt, the interrupt becomes disabled after execution of the
clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and
the interrupt is requested during execution of that instruction, at the instant when the instruction
ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-
handling sequence is executed for the interrupt. If a higher-priority interrupt is requested at the
same time, however, the hardware exception-handling sequence is executed for the higher-priority
interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to “0.”
Figure 4.7 shows an example in which the OCIAE bit is cleared to “0.”
Ø
Internal address bus
OCIAE
OCIA interrupt handling
OCIA interrupt signal
OCFA
CPU write
cycle to TIER
Internal write signal
TIER address
Figure 4.7 Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to “0” while the interrupt
mask bit (I) is set to “1.”