Hardware manual

Rev. 3.0, 09/98, page 73 of 361
Internal address
bus
Internal Read
signal
Internal Write
signal
Internal 16-bit
data bus
Ø
Interrupt request
signal
(2) (4) (1) (7) (9) (10)
(8)(6)(5)(3)(1) (9)
Stack Vector fetch
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
interrupt-handling routine.)
Instruction code (Not executed)
Instruction prefetch address (Not executed)
SP-2
(1)
(2) (4)
(3)
(5)
SP-4
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
(6)
(7)
(8)
(9)
(10)
Interrupt priority
decision. Wait for
end of instruction.
Instruction fetch
(first instruction of
interrupt-handling
routine)
Internal
processing
Internal
processing
Instruction fetch
Interrupt
accepted
Figure 4.6 Timing of Interrupt Sequence