Hardware manual

Rev. 3.0, 09/98, page 67 of 361
Bits 0 to 7IRQ
0
to IRQ
7
Sense Control (IRQ
0
SC to IRQ
7
SC): These bits determine whether
IRQ
0
to IRQ
7
are level-sensed or sensed on the falling edge.
Bits 0 to 7
IRQ
0
SC to IRQ
7
SC Description
0 An interrupt is generated when IRQ
0
to IRQ
7
(Initial state)
inputs are Low.
1 An interrupt is generated by the falling edge of the IRQ
0
to IRQ
7
inputs.
IRQ Enable Register (IER)H'FFC7
Bit:76543210
IRQ
7
EIRQ
6
EIRQ
5
EIRQ
4
EIRQ
3
EIRQ
2
EIRQ
1
EIRQ
0
E
Initial value:00000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0 to 7IRQ
0
to IRQ
7
Enable (IRQ
0
E to IRQ
7
E): These bits enable or disable the IRQ
0
to
IRQ
7
interrupts individually.
Bits 0 to 7
IRQ
0
E to IRQ
7
E Description
0 IRQ
0
to IRQ
7
interrupt requests are disabled. (Initial state)
1 IRQ
0
to IRQ
7
interrupt requests are enabled.
When edge sensing is selected (by setting bits IRQ
0
SC to IRQ
7
SC to “1”), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ
0
E to
IRQ
7
E) is cleared to “0” and the interrupt is disabled. If an interrupt is requested while the enable
bit (IRQ
0
E to IRQ
7
E) is set to “1,” the request will be held pending until served. If the enable bit is
cleared to “0” while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to “0,” the
interrupt-handling routine can be executed even though the enable bit is now “0.”
If execution of interrupt-handling routines under these conditions is not desired, it can be avoided
by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to “1” in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
when execution jumps to an interrupt vector.
2. Clear the desired bits from IRQ
0
E to IRQ
7
E to “0” to disable new interrupt requests.
3. Clear the corresponding IRQ
0
SC to IRQ
7
SC bits to “0,” then set them to “1” again. Pending
IRQn interrupt requests are cleared when I = “1” in the CCR, IRQnSC = “0,” and IRQnE =
“0.”