Hardware manual

Rev. 3.0, 09/98, page 66 of 361
4.3.2 Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), and IRQ enable register (IER).
Table 4.3 Registers Read by Interrupt Controller
Name Abbreviation Read/write Address
System control register SYSCR R/W H'FFC4
IRQ sense control register ISCR R/W H'FFC6
IRQ enable register IER R/W H'FFC7
System Control Register (SYSCR)H'FFC4
Bit:76543210
SSBY STS2 STS1 STS0  NMIEG DPME RAME
Initial value:00001001
Read/Write: R/W R/W R/W R/W  R/W R/W R/W
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2
NMIEG Description
0 An interrupt is generated on the falling edge of NMI. (Initial state)
1 An interrupt is generated on the rising edge of NMI.
See section 2.2, “System Control Register,” for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)H'FFC6
Bit:76543210
IRQ
7
SC IRQ
6
SC IRQ
5
SC IRQ
4
SC IRQ
3
SC IRQ
2
SC IRQ
1
SC IRQ
0
SC
Initial value:00000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W