Hardware manual

Rev. 3.0, 09/98, page 64 of 361
4.2.3 Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7),
the program counter and condition code register might not be saved correctly, leading to a
program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a
reset. The first program instruction is therefore always executed. This instruction should initialize
the stack pointer (example: MOV.W #xx:16, SP).
4.3 Interrupts
4.3.1 Overview
The interrupt sources include nine input pins for external interrupts (NMI, IRQ
0
to IRQ
7
) and 22
internal sources in the on-chip supporting modules. Table 4.2 lists the interrupt sources in priority
order and gives their vector addresses. When two or more interrupts are requested, the interrupt
with highest priority is served first.
The features of these interrupts are:
• NMI has the highest priority and is always accepted. All internal and external interrupts except
NMI can be masked by the I bit in the CCR. When the I bit is set to “1,” interrupts other than
NMI are not accepted.
• IRQ
0
to IRQ
7
can be sensed on the falling edge of the input signal, or level-sensed. The type of
sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the
rising or falling edge can be selected.
• All interrupts are individually vectored. The software interrupt-handling routine does not have
to determine what type of interrupt has occurred.