Hardware manual

Rev. 3.0, 09/98, page 61 of 361
Section 4 Exception Handling
4.1 Overview
The H8/338 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4.1
indicates their priority and the timing of their hardware exception-handling sequence.
Table 4.1 Hardware Exception-Handling Sequences and Priority
Priority
Type of
Exception Timing of Exception-Handling Sequence
Reset The hardware exception-handling sequence begins as soon as RES
changes from Low to High.
High
Low
Interrupt When an interrupt is requested, the hardware exception-handling
sequence begins at the end of the current instruction, or at the end of
the current hardware exception-handling sequence.
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the RES pin goes Low, all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. When RES returns from Low to High, the reset
exception-handling sequence starts.
4.2.2 Reset Sequence
The reset state begins when RES goes Low. To ensure correct resetting, at power-on the RES pin
should be held Low for at least 20ms. In a reset during operation, the RES pin should be held Low
for at least 10 system clock cycles. For the pin states during a reset, see appendix C, “Pin States.”
When RES returns from Low to High, hardware carries out the following reset exception-handling
sequence.
(1) The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit in the condition code register (CCR) is set to “1.”
(2) The CPU loads the program counter with the first word in the vector table (stored at addresses
H'0000 and H'0001) and starts program execution.
The RES pin should be held Low when power is switched off, as well as when power is switched
on.