Hardware manual

Rev. 3.0, 09/98, page 49 of 361
2.7.2 Access to On-Chip Register Field and External Devices
The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.)
and external devices are accessed in a cycle consisting of three states: T
1
, T
2
, and T
3
. Only one
byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction
codes requires two consecutive cycles (six states).
Figure 2.15 shows the access cycle for the on-chip register field. Figure 2.16 shows the associated
pin states. Figures 2.17 (a) and (b) show the read and write access timing for external devices.
Ø
Internal address bus
Internal Read signal
Internal data bus
(read)
Internal Write signal
Internal data bus
(write)
Bus cycle
T1 state T2 state
Address
T3 state
Read data
Write data
Figure 2.15 On-Chip Register Field Access Cycle