Hardware manual

Rev. 3.0, 09/98, page 47 of 361
2.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (φ). The period from one rising edge of the system clock
to the next is referred to as a “state.”
Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip
supporting modules, and external devices are accessed in different bus cycles as described below.
2.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T
1
and T
2
. Either byte or
word data can be accessed, via a 16-bit data bus. Figure 2.13 shows the on-chip memory access
cycle. Figure 2.14 shows the associated pin states.
Ø
Internal address bus
Internal Read signal
Internal data bus
(read)
Internal data bus
(write)
Internal Write signal
Bus cycle
T1 state T2 state
Read data
Write data
Address
Figure 2.13 On-Chip Memory Access Cycle