Hardware manual

Rev. 3.0, 09/98, page 45 of 361
Program
execution state
Exception-
handling state
Interrupt request
NMI or IRQ0
to IRQ2
SLEEP instruction
with SSBY bit set
SLEEP
instruction
Power-down state
RES= 1
STBY= 1, RES= 0
Exception
handing
Exception
handing
request
Reset state
Sleep mode
Software
standby mode
Hardware
standby mode
Notes: 1.
2.
A transition to the reset state occurs when RES goes Low, except when
the chip is in the hardware standby mode.
A transition from any state to the hardware standby mode occurs when
STBY goes Low.
Figure 2.12 State Transitions
2.6.1 Program Execution State
In this state the CPU executes program instructions.
2.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
(1) Saves the program counter and condition code register to the stack (except in the case of a
reset).
(2) Sets the interrupt mask (I) bit in the condition code register to “1.”
(3) Fetches the start address of the exception-handling routine from the vector table.
(4) Branches to that address, returning to the program execution state.
See section 4, “Exception Handling,” for further information on the exception-handling state.