Hardware manual

Rev. 3.0, 09/98, page 37 of 361
Before Execution of BCLR Instruction
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
DDR 00111111
DR 10000000
Execution of BCLR Instruction
BCLR #0, @P4DDR ;clear bit 0 in data direction register
After Execution of BCLR Instruction
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High
DDR 11111110
DR 10000000
Explanation:
To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4
0
DDR is cleared to “0,” making P4
0
an input pin. In addition, P4
7
DDR and P4
6
DDR
are set to “1,” making P4
7
and P4
6
output pins.