Hardware manual

Rev. 3.0, 09/98, page 358 of 361

Appendix D Timing of Transition to and Recovery from

Hardware Standby Mode

Timing of Transition to Hardware Standby Mode

(1) To retain RAM contents when the RAME bit in SYSCR is cleared to 0, drive the

RES signal

low 10 system clock cycles before the STBY signal goes low, as shown below. RES must

remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).

STBY

RES

t 10 t

≥

cyc

t 0 ns

≥

(2) When the RAME bit in SYSCR is set to “1” or when it is not necessary to retain RAM

contents, RES does not have to be driven low as in (1).

Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately

100 ns before STBY goes high.

STBY

RES

t 100 ns

≥

OSC