Hardware manual

Rev. 3.0, 09/98, page 356 of 361
Appendix C Pin States
C.1 Pin States in Each Mode
Table C.1 Pin States
Pin Name
MCU
Mode Reset
Hardware
Standby
Software
Standby Sleep Mode
Normal
Operation
1 Low 3-State Low A
7
− A
0
P1
7
− P1
0
A
7
− A
0
2 3-State Low if DDR = 1,
Prev. state
if DDR = 0
Prev. state
(Addr. output
pins: last address
accessed)
Addr. output or
input port
3 Prev. state I/O port
1 Low 3-State Low A15 − A8P2
7
− P2
0
A1
5
− A
8
2 3-State Low if DDR = 1,
Prev. state
if DDR = 0
Prev. state
(Addr. output
pins: last address
accessed)
Addr. output or
input port
3 Prev. state I/O port
1 3-State 3-State 3-state 3-State D
7
− D
0
P3
7
− P3
0
D
7
− D
0
2
3 Prev. state Prev. state I/O port
P4
7
− P4
0
1
2
3
3-State 3-State Prev. state
*
Prev. state I/O port
P5
2
− P5
0
1
2
3
3-State 3-State Prev. state
*
Prev. state I/O port
Notes: 1. 3-State: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may
also be used by the on-chip supporting modules.
See section 5, “I/O Ports,” for further information.
*
On-chip supporting modules are initialized, so these pins revert to I/O ports according to
the DDR and DR bits.