Hardware manual

Rev. 3.0, 09/98, page 350 of 361
SCRSerial Control Register H'FFDA SCI0
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Clock enable 0
0 Asynchronous serial clock not output
Asynchronous serial clock output at
SCK pin
1
Clock Enable 1
0 Internal clock
External clock
1
Transmit End Interrupt Enable
0 TSR-empty interrupt request is disabled.
TSR-empty interrupt request is enabled.
1
Multiprocessor Interrupt Enable
0 Multiprocessor receive interrupt function is disabled.
Multiprocessor receive interrupt function is enabled.
1
Receive Enable
0 Receive disabled
Receive enabled
1
Transmit Enable
0 Transmit disabled
Transmit enabled
1
Receive Interrupt Enable
0 Receive interrupt and receive error interrupt requests are disabled.
Receive interrupt and receive error interrupt requests are enabled.
1
Transmit Interrupt Enable
0 TDR-empty interrupt request is disabled.
TDR-empty interrupt request is enabled.
Note: Bit functions are the same as for SCI1.
1