Hardware manual

Rev. 3.0, 09/98, page 346 of 361
TCRTimer Conrol Register H'FFD0 TMR1
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select
CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 — — Timer stopped
0 0 1 0 — Ø/8 internal clock, falling edge
0 0 1 1 — Ø/2 internal clock, falling edge
0 1 0 0 — Ø/64 internal clock, falling edge
0 1 0 1 — Ø/128 internal clock, falling edge
0 1 1 0 — Ø/1024 internal clock, falling edge
0 1 1 1 — Ø/2048 internal clock, falling edge
1 0 0 — — Timer stopped
1 0 1 — — External clock, rising edge
1 1 0 — — External clock, falling edge
1 1 1 — — External clock, rising and falling
edges
TCR STCR
Compare-Match Interrupt Enable A
0 Compare-match A interrupt request is disabled.
Compare-match A interrupt request is enabled.
1
Compare-Match Interrupt Enable B
0 Compare-match B interrupt request is disabled.
Compare-match B interrupt request is enabled.
Counter Clear
0 0 Counter is not cleared.
0 1 Cleared by compare-match A.
1 0 Cleared by compare-match B.
1 1 Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
0
1
1