Hardware manual

Rev. 3.0, 09/98, page 344 of 361
TCSRTimer Control/Status Register H'FFC9 TMR0
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
1
6
CMFA
0
R/(W)*
1
5
OVF
0
R/(W)*
1
4
—
1
—
3
OS3*
2
0
R/W
0
OS0*
2
0
R/W
2
OS2*
2
0
R/W
1
OS1*
2
0
R/W
Output Select
0 0 No change on compare-match A.
0 1 Output “0” on compare-match A.
1 0 Output “1” on compare-match A.
1 1 Invert (toggle) output on compare-match A.
Output Select
0 0 No change on compare-match B.
0 1 Output “0” on compare-match B.
1 0 Output “1” on compare-match B.
1 1 Invert (toggle) output on compare-match B.
Compare-Match Flag A
0
Notes: 1.
2.
Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
Cleared when CPU reads CMFA = “1,” then writes “0” in CMFA.
Set when TCNT = TCORA.
1
Compare-Match Flag B
0 Cleared from when CPU reads CMFB = “1,” then writes “0” in CMFB.
Set when TCNT = TCORB.
1
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
Set when TCNT changes from H'FF to H'00.
1