Hardware manual
Rev. 3.0, 09/98, page 342 of 361
MDCRMode Control Register H'FFC5 System Control
Bit
Initial value
Read/Write
Note: * Determined by inputs at pins MD
1
and MD
0
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
—
3
—
0
—
0
MDS
0
*
R/W
2
—
1
—
1
MDS
1
*
R/W
Mode Select Bits
Value at mode pins.
ISCRIRQ Sense Control Register H'FFC6 System Control
Bit
Initial value
Read/Write
7
IRQ
7
SC
0
R/W
6
IRQ
6
SC
0
R/W
5
IRQ
5
SC
0
R/W
4
IRQ
4
SC
0
R/W
3
IRQ
3
SC
0
R/W
0
IRQ
0
SC
0
R/W
2
IRQ
2
SC
0
R/W
1
IRQ
1
SC
0
R/W
IRQ
0
to IRQ
7
Sense Control
IRQi is level-sensed (active low).
IRQi is edge-sensed (falling edge).
0
1
IERIRQ Enable Register H'FFC7 System Control
Bit
Initial value
Read/Write
7
IRQ
7
E
0
R/W
6
IRQ
6
E
0
R/W
5
IRQ
5
E
0
R/W
4
IRQ
4
E
0
R/W
3
IRQ
3
E
0
R/W
0
IRQ
0
E
0
R/W
2
IRQ
2
E
0
R/W
1
IRQ
1
E
0
R/W
IRQ
0
to IRQ
7
Enable
IRQi is disabled.
IRQi is enabled.
0
1